RFRST=0, TTRG=others, FM=0, RSTRG=others, DRES=0, TFRST=0, RTRG=others
FIFO Control Register
| FM | FIFO Mode Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 0 (0): Non-FIFO mode 1 (1): FIFO mode |
| RFRST | Receive FIFO Data Register Reset(Valid only in FCR.FM=1) 0 (0): The number of data stored in FRDRH and FRDRL register are NOT made 0 1 (1): The number of data stored in FRDRH and FRDRL register are made 0 |
| TFRST | Transmit FIFO Data Register Reset(Valid only in FCR.FM=1) 0 (0): The number of data stored in FTDRH and FTDRL register are NOT made 0 1 (1): The number of data stored in FTDRH and FTDRL register are made 0 |
| DRES | Receive data ready error select bit(When detecting a reception data ready, the interrupt request is selected.) 0 (0): reception data full interrupt (RXI) 1 (1): receive error interrupt (ERI) |
| TTRG | Transmit FIFO data trigger number(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 0 (0000): Trigger number 0 0 (others): Triger number n (n= 0-15) |
| RTRG | Receive FIFO data trigger number 0 (0000): Trigger number 0 0 (others): Triger number n (n= 0-15) |
| RSTRG | RTS# Output Active Trigger Number Select(Valid only in asynchronous mode(including multi-processor) or clock synchronous mode) 0 (0000): Trigger number 0 0 (others): Triger number n (n= 0-15) |